A clock and data recovery (CDR) circuit can be used to recover information from a stream of data when the data is received without an accompanying clock. The CDR circuit can include a clock recovery circuit to provide a clock that is aligned to the data. Optimal sampling of the data to recover information from the data can be performed when the clock is correctly aligned to the data.
The CDR circuit may employ a negative feedback loop (e.g., phase lock loop) to generate a clock whose phase is aligned to the phase of the data. The negative feedback loop may include a phase detector, a loop filter and a phase adjuster (e.g., voltage controlled oscillator). The phase detector may receive a clock (e.g., sampling clock) and a data stream as inputs and output a signal representing a phase difference (e.g., phase error) between the clock and the data. The loop filter may process the signal representing the phase difference and provide a filtered signal to the phase adjuster. The phase adjuster may use the filtered signal to adjust the clock to align the phase of the clock to the phase of the data.
The phase detector can be a linear phase detector or a bang-bang phase detector (e.g., non-linear phase detector or binary phase detector). Linear phase detectors generate outputs that have a linear (or proportional) relationship to phase differences at the inputs. As the magnitude of the phase difference changes, the magnitude of the linear phase detector output changes proportionally. The output of a linear phase detector will be zero when the clock and the data are synchronized. Bang-bang phase detectors generate outputs that have a step function relationship to a phase difference at their inputs. Thus, bang-bang phase detectors merely provide a positive or a negative pulse indicating whether the phase of the clock is leading or lagging the phase of the data and do not provide information about the magnitude of the phase difference at the inputs. The output of a bang-bang detector will alternate between a positive and a negative signal when the clock and the data are phase aligned.
Because each of these phase detectors have their advantages and disadvantages, they are used based on the performance requirements of the application. Linear phase detectors sometimes are preferred over bang-bang phase detectors because linear phase detectors generate less charge pump activity and have lower ripple on the CDR circuit resulting in less timing jitter. However, due to the finite gain of the linear phase detectors, any dc offset errors that are injected at the output of the linear phase detector will be reflected back to the input as constant (static) phase errors between the clock and the data. The presence of this static phase error between the clock and the data can lead to a sub-optimal sampling point for the data in the CDR circuit. As a result, the presence of the static phase error can degrade performance when the input data has significant jitter (i.e., phase movement).
The static phase error may be due to a delay caused by one or more of the components in the phase detector. Calibration can be used to improve the performance of a linear phase detector by correcting for the static phase error caused by the linear phase detector. The static phase error caused by the linear phase detector may be compensated for by changing a parameter of the linear phase detector or a parameter of the CDR circuit (e.g., adding an offset value to the phase detector output). Existing calibration methods do not always provide accurate results and can involve using complex circuits to perform the calibration process. These circuits include many components which are only used for the calibration and are not utilized when the clock is aligned with the data stream.
The inventors have identified a need in the art for a simple method and circuit that can be used to calibrate the phase detector and/or the CDR circuit to correct for the static phase error.